The use of MOS floating gate storage devices in semiconductor memories has increased rapidly in recent years. A typical MOS floating gate storage device includes a floating gate structure disposed over the surface of a semiconductor substrate between spacedapart source and drain regions. A control gate is then vertically aligned with the floating gate. In order to program the storage device, a potential is applied to the control gate, causing charge carriers to travel from the semiconductor substrate to the floating gate, and in the process modifying the threshold voltage in the channel region established between the spacedapart source and drain regions. During read operations, the presence or absence of charge carriers on the floating gate can be determined in binary fashion by simply measuring the presence or absence of current flow through the storage device channel region in response to voltage potentials applied to the storage device drain region. When floating gate storage devices of the type described above are incorporated in an EEPROM memory array, individual floating gates are defined for each storage device, but a single conductive strip may be deposited and etched to define the control gates for all of the storage devices comprising an individual byte. Such a conductive strip is commonly known as a sense line. Sense lines are uniquely decoded for every individual byte by a combination of x and y decoder. A word line (x-line) is another conductive strip comprising a single row in the memory array and designation of a praticular row of x-address in the memory array serves to enable the word line associated with the x-address in preparation for the memory array programming or read operation.
Because the amount of time required to program any individual storage device located along a given word line depends upon the amount of charge applied to the storage device floating gate, the ability to increase the voltage present on the associated word line during memory programming operations, and thus provide a greater charge enables programming times to be signficantly reduced.
In prior art memory arrays, each word line is generally connected to an external high voltage supply through a single small depletion pull-up device which terminates in a pin to the outside of the memory, usually designated Vpp. The depletion device is activated when programming is desired to apply the voltage from the external high voltage supply to a selected word line.
The number of word lines in any given memory array varies with the size of the array. For example, in a 16 K-bit memory arranged in a 128.times.128 bit array, there are 128 x-lines or word lines. Since only one word line is selected for programming any one byte, there are 127 unselected word lines during any program cycle.
In prior art memory arrays, unselected word lines are held low, or at ground potential, through pull-down devices provided in their associated decoder sections. A DC current path exists between Vpp and ground for all unselected word lines. This current through the 127 unselected word lines in a 128.times.128 bit array constitutes a drain on the external high voltage supply in the multi-milliampere range.
The recent trend towards the provision of selfaltering intelligent systems has created a need for memory devices which do not require external high voltage power supplies for programming. However, voltages higher than the standard 5 volt power supplies are still necessary for programming purposes. It has been proposed that these higher voltages necessary to achieve acceptable programming times be generated on the memory chip itself. Circuits for voltage multiplication readily adaptable to integration on a memory array chip have been proposed. However, in order for capacitor sizes in those circuits to be reasonably sized for practical integration on a memory array chip, current drive capabilities must be sacrificed. Consequently, such on-chip high voltage generation techniques cannot be implemented where conventional programming circuits are used, especially in larger arrays, since the DC current leakage through the unselected word lines would cause an unacceptable current drain on the high voltage generation circuit, causing its voltage to drop drastically.